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| September 1995 Edition 4.0a DATA SHEET MB1507 SERIAL INPUT PLL FREQUENCY SYNTHESIZER SERIAL INPUT PLL FREQUENCY SYNTHESIZER WITH 2.0GHZ PRESCALER The Fujitsu MB1507 is a single chip serial input PLL frequency synthesizer designed for Broadcast Satelite tuner and cellular telephone applications. It contains a 2.0 GHZ dual modulus prescaler which enables pulse swallow function, and an analog switch to speed up lock up time. It operates supply voltage of 5.0V typ. and dissipates 18mA typ. of current realized through the use of Fujitsu's unique U-ESBIC Bi-CMOS technology. * * * * * * * * * High operating frequency: fIN MAX=2.0GHZ (PIN MIN=-4dBm) Pulse swallow function: 128/129 or 256/257 Low supply current: ICC=18mA typ. Serial input 19-bit programmable divider consisting of: Binary 8-bit swallow counter: 0 to 255 Binary 11-bit programmable counter: 16 to 2047 Serial input 15-bit programmable reference divider consisting of: Binary 14-bit programmable reference counter: 8 to 16383 1-bit switch counter (SW) Sets divide ratio of prescaler On-chip analog switch achieves fast lock up time 2types of phase detector output On-chip charge pump (Bipolar type) Output for external charge pump Wide operating temperature: -40C to +85C 16-pin Plastic Flat Package (Suffix: -PF) OSCIN OSCOUT VP VCC 1 2 3 4 TOP VIEW DO 5 6 7 8 12 11 10 9 FC LE Data Clock 16 15 14 13 OR OP fOUT BISW PLASTIC PACKAGE FPT-16P-M06 PIN ASSIGNMENT ABSOLUTE MAXIMUM RATINGS (see NOTE) Rating Power Supply Voltage Output Voltage Open-drain Voltage Output Current Storage Temperature NOTE: Symbol VCC VP VOUT VOOP IOUT TSTG Value -0.5 to +7.0 VCC to 10.0 -0.5 to VCC +0.5 -0.5 to 8.0 +10 -55 to +125 Unit V V V V mA GND LD fIN C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Copyright(c) 1995 FUJITSU LIMITED and FUJITJU MICROELECTRONICS, INC. 1 MB1507 MB1507 BLOCK DIAGRAM OSCIN 1 CRYSTAL OSCILLATOR 16-BIT SHIFT REGISTER 16-BIT SHIFT REGISTER PHASE COMPARATOR 16 OR OSCOUT 2 15-BIT LATCH MONITOR FREQUENCY CHANGING CIRCUIT ANALOG SWITCH 15 OP VP 3 15-BIT LATCH 14 fOUT VCC 4 PROGRAMMABLE REFERENCE DIVIDER BINARY 14-BIT REFERENCE COUNTER S W CHARGE PUMP fr 13 BISW DO LE 12 FC DO 5 GND 6 11 LE LD 7 20-BIT SHIFT REGISTER 20-BIT SHIFT REGISTER CONTROL 1-BIT LATCH 10 Data 9 19-BIT LATCH 8-BIT LATCH 11-BIT LATCH Clock fIN 8 PRESCALER PROGRAMMABLE DIVIDER BINARY 8-BIT SWALLOW COUNTER BINARY 11-BIT PROGRAMMABLE COUNTER fp CONTROL CIRCUIT 2 MB1507 PIN DESCRIPTION Pin No. 1 2 Pin Name OSCIN OSCOUT I/O I O Description Oscillator input. Oscillator output. A crystal is placed between OSCIN and OSCOUT. Power supply input for charge pump and analog switch. Power supply voltage input. Charge pump output. The characteristics of charge pump is reversed depending upon FC input. Ground. Phase comparator output. Normally the output level is high level. While the phase difference of fr and fp exists, the output becomes low level. Prescaler input. The connection with VCO should be AC connection. Clock input for 20-bit shift register and 16-bit shift register. On rising edge of the clock shifts one bit of data into the shift registers. Binary serial data input. The last bit of the data is a control bit which specified destination of shift registers. When this bit is high level and LE is high level, the data stored in shift register is transferred to 15-bit latch. When this bit is low level and LE is high level, the data is transferred to 19-bit latch. Load enable input (with pull up resistor). When LE is high or open, the data stored in shift register is transferred into latch depending upon the control bit. At the time, internal charge pump output to be connected to BISW pin because internal analog switch becomes ON state. Phase select input of phase comparator (with pull up resistor). When FC is low level, the characteristics of charge pump, phase comparator is reversed. FC pin input signal controls fout pin (test pin) output level, fr or fp. Analog switch output. Usually BISW pin is set high-impedance state. When internal analog switch is ON (LE pin is high level), this pin outputs internal charge pump output. Monitor pin of phase comparator input. fout pin outputs programmable reference divider output (fr) or programmable divider output (fp) depending upon FC pin input level. FC=H: It is the same as fr output level. FC=L: It is the same as fp output level. Outputs for external charge pump. The characteristics are reversed according to FC input. P pin is N-channel open drain output. 3 4 5 6 VP VCC DO GND - - O - 7 LD O 8 fIN I 9 Clock I 10 Data I 11 LE I 12 FC I 13 BISW O 14 fOUT O 15 16 OP OR O O 3 MB1507 FUNCTIONAL DESCRIPTIONS SERIAL DATA INPUT Serial data input is achieved by three inputs, such as Data pin, Clock pin and LE pin. Serial data input controls 15-bit programmable reference divider and 19-bit programmable divider, respectively. Binary serial data is input to Data pin. On rising edge of clock shifts one bit of serial data into the internal shift registers and when load enable pin is high level or open, stored data is transferred into latch depending upon the control bit. Control data "H" data is transferred into 15-bit latch. Control data "L" data is transferred into 19-bit latch. THE DIVIDE RATIO SETTING fVCO=[(MxN)+A]xfOSC/R fVCO: Output frequency of external voltage controlled oscillator (VCO) M: Preset modulus of external dual modulus prescaler (128 or 256) N: Preset divide ratio of binary 11-bit programmable counter (16 to 2047) A: Preset divide ratio of binary 8-bit swallow counter (0A255, A Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit reference counter. Serial 16-bit data format is shown below. Control bit LSB C S 1 S 2 S 3 S 4 S 5 S 6 S 7 Divide ratio of prescaler setting bit MSB S 8 S 9 S 10 S 11 S 12 S 13 S 14 S W Divide ratio of programmable reference counter setting bit 14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO Divide Ratio R 8 9 S 14 0 0 S 13 0 0 S 12 0 0 S 11 0 0 S 10 0 0 S 9 0 0 S 8 0 0 S 7 0 0 S 6 0 0 S 5 0 0 S 4 1 1 S 3 0 0 S 2 0 0 S 1 0 1 * 16383 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 NOTES: Divide ratio less than 8 is prohibited. Divide ratio: 8 to 16383 SW: This bit selects divide ratio of prescaler. SW=H : 128/129 SW=L : 256/257 S1 to S14: These bits select divide ratio of programmable reference divider. C: Control bit (sets as high level). Data is input from MSB side. 4 MB1507 PROGRAMMABLE DIVIDER Programmable divider consists of 20-bit shift register, 19-bit latch, 8-bit swallow counter and 11-bit programmable counter. Serial 20-bit data format is shown below. Control bit LSB C S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S 10 S 11 S 12 S 13 S 14 S 15 MSB S 16 S 17 S 18 S 19 Divide ratio of swallow counter setting bit Divide ratio of programmable counter setting bit 8-BIT SWALLOW COUNTER DIVIDE RATIO Divide Ratio A 0 1 S 8 0 0 S 7 0 0 S 6 0 0 S 5 0 0 S 4 0 0 S 3 0 0 S 2 0 0 S 1 0 1 * 255 NOTE: * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 Divide ratio: 0 to 255 11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO Divide Ratio N 16 17 S 19 0 0 S 18 0 0 S 17 0 0 S 16 0 0 S 15 0 0 S 14 0 0 S 13 1 1 S 12 0 0 S 11 0 0 S 10 0 0 S 9 0 1 * 2047 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 NOTES: Divide ratio less than 16 is prohibited. Divide ratio: 16 to 2047 S1 to S8: Swallow counter divide ratio setting bit. (0 to 255) S9 to S19: Programmable counter divide ratio setting bit. (16 to 2047) C: Control bit (sets to low level). Data is input from MSB side. 5 MB1507 SERIAL DATA INPUT TIMING t1, t2, t3, t4, t51s Data S19=MSB *(SW) Clock S18 (S14) S11 S10 (S7) (S6) S1=LSB (S1) C: CONTROL BIT (C: CONTROL BIT) LE t1 t2 t3 t4 t5 NOTES: Parenthesis data is used for setting divide ratio of programmable reference divider. On rising edge of clock shifts one bit of data into the shift register. PHASE CHARACTERISTICS VCO POLARITY FC pin is provided to change phase polarity of phase comparator. Characteristics of internal charge pump output level (DO), phase comparator output level VCO OUTPUT FREQUENCY (OR, OP) are reversed depending upon FC pin input level. Also, monitor pin (fout) output level of phase comparator is controlled by FC pin input level. 1 FC=H or open DO fr>fp fr=fp fr 2 VCO INPUT VOLTAGE Z=(High impedance) Depending upon VCO polarity, FC pin should be set accordingly: When VCO polarity are like 1 , FC should be set High or open circuit; When VCO polarity are like 2 , FC should be set Low. 6 MB1507 PHASE DETECTOR OUTPUT WAVEFORM (FC=High) fr fP LD H DO fr>fp fr=fp Z L fr ON/OFF of analog switch is controlled by LE input signal. When the analog switch is ON, internal charge pump output (DO) is connected to BISW pin. When the analog switch is OFF, BI-SW pin is set to high-impedance state. LE H(Changing the divide ratio of internal prescaler) L(Normal operating mode) Analog Switch ON OFF When an analog switch is inserted between LP1 and LP2, faster lock up time is achieved to reduce LPF time constant during PLL channel switching. DO CHARGE PUMP LPF-1 LPF-2 VCO ANALOG SW BISW (CONTROL SIGNAL LE) 7 MB1507 RECOMMENDED OPERATING CONDITIONS Value Parameter Symbol Min VCC Power Supply Voltage VP Input Voltage Operating Temperature VI TA VCC GND -40 -- -- -- 8.0 VCC 85 V V 4.5 Typ 5.0 Max 5.5 V Unit C HANDLING PRECAUTIONS * * * * This device should be transported and stored in anti-static containers. This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats. Always turn the power supply off before inserting or removing the device from its socket. Protect leads with a conductive sheet when handling or transporting PC boards with devices. 8 MB1507 ELECTRICAL CHARACTERISTICS Parameter Power Supply Current fin Operating Frequency OSCIN fin Input Sensitivity OSCIN High-level Input Voltage Low-level Input Voltage High-level Input Current Low-level Input Current Except fin and OSCIN VOSC VIH VIL IIH IIL IOSC ILE VOH VCC=5V VOL IOFF IOH IOL RON VP=VCC to 8V VOOP=GND to 8V -- -- -- -- -- -1.0 1.0 -- -- -- -- -- 25 0.4 1.1 -- -- -- V -- -- -- -- -- -- -- 0.5 VCCx0.7 -- -- -- -- -- 4.4 -- -- -- 1.0 -1.0 "50 -60 -- -- -- VCCx0.3 -- -- -- -- -- VPP V V fOSC Pfin -- 50 -- -4 12 -- 20 6 MHz dBm Symbol ICC fin Condition Note 1 Note 2 Value Min -- 10 Typ 18.0 -- Max -- 2000 Unit mA MHz Data Clock A A A A V OSCIN Input Current LE, FC High-level Output Current Low-level Output Current High Impedance Cutoff Current Except DO and OSCOUT DO, OP A mA mA Output Current Except DO and OSCOUT Analog Switch On Resistance NOTE 1: fin=2.0GHz, fOSC =12MHz X'tal VCC=5V. Inputs are grounded and outputs are open. NOTE 2: AC coupling. Minimum operating frequency is measured with a capacitor 1000PF. 9 MB1507 TEST CIRCUIT (Prescaler Input Sensitivity) VCC=5V Vp=6V 0.1F 1000pF P*G 50 8 7 6 5 4 3 2 X'tal 1 MB1507 9 10 11 12 13 14 15 16 Oscilloscope 10 MB1507 TYPICAL APPLICATION EXAMPLE VPX(6V) LPF 10k Charge Pump Selection (Internal or external) FROM CONTROLLER 10k VCO OUTPUT 12k 12k OR 16 15 OP 14 fOUT 13 BISW 12 FC 11 LE 10 Data 9 Clock 47k 47k MB1507 1 OSCIN 2 3 OSCOUT Vp 4 VCC 5 DO 6 GND 7 LD 8 fin X'tal 1000p VCC(5V) 6V C1 C2 5V 100k 33k 0.1 0.01 Vp, VPX : C1, C2 : LE,FC : OP : 8V max. Depends on crystal oscillator With pull up resistor Open drain output 10k LOCK DETECTOR 11 MB1507 PACKAGE DIMENSIONS 16-LEAD PLASTIC FLAT PACKAGE (Case No. : FPT-16P-M06) +0.25 ) .400 +.010 (10.15 -0.20 -.008 .089(2.25)MAX (MOUNTING HEIGHT) .002(0.05)MIN (STAND OFF HEIGHT) INDEX "B" .307.016 (7.800.40) .209.012 (5.300.30) .268+.016(6.80+0.40 ) -0.20 -.008 .020.008 (0.500.20) .050(1.27) TYP .018.004 (0.450.10) "A" O.005(0.13) M .006+.002(0.15 +0.05 ) -0.02 -.001 Details of "B" part .006(0.15) Details of "A" part .016(0.40) .004(0.10) .350(8.89) REF (c)1991 FUJITSU LIMITED F16015S-2C .008(0.20) .007(0.18) MAX .027(0.68) MAX .008(0.20) .007(0.18) MAX .027(0.68) MAX Dimensions in inches (millimeters) 12 MB1507 All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete Information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The Information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. 13 MB1507 For further information please contact: Japan FUJITSU LIMITED Electronic Devices International Operations Department KAWASAKI PLANT, 1015 Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 211, Japan Tel: (044) 754-3753 FAX: (044) 754-3332 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 FAX: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10, 63303 Dreieich-Buchschlag, Germany Tel: (06103) 690-0 FAX: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LIMITED No.51 Bras Basah Road, Plaza By The Park, #06-04 to #06-07 Singapore 0718 Tel: 336-1600 FAX: 336-1609 I9501 (c) FUJITSU LIMITED Printed in Japan 14 |
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